Yu U Zhao

US Patent:

8072272, Dec 6, 2011

Filed:

Mar 1, 2010

Appl. No.:

12/715254

Inventors:

Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Aristotele Hadjichristos - San Diego CA, US

Assignee:

QUALCOMM, Incorporated - San Diego CA

International Classification:

H03F 3/04

US Classification:

330310, 330302

Abstract:

A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus includes a first active circuit (e. g. , a driver amplifier), a second active circuit (e. g. , a power amplifier), and a tunable inter-stage matching circuit coupled between the first and second active circuits. The tunable inter-stage matching circuit includes a tunable capacitor that can be varied in discrete steps to adjust impedance matching between the first and second active circuits. In an exemplary design, the tunable capacitor includes (i) a plurality of capacitors coupled in parallel and (ii) a plurality of switches coupled to the plurality of capacitors, one switch for each capacitor. Each switch may be turned on to select an associated capacitor or turned off to unselect the associated capacitor. The tunable capacitor may further include a fixed capacitor coupled in parallel with the plurality of capacitors.

US Patent:

8536950, Sep 17, 2013

Filed:

Dec 17, 2009

Appl. No.:

12/641228

Inventors:

Babak Nejati - San Diego CA, US
Yu Zhao - San Diego CA, US
Nathan M Pletcher - Encinitas CA, US
Aristotele Hadjichristos - San Diego CA, US
Puay Hoe See - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03F 3/04

US Classification:

330302, 330 51

Abstract:

Exemplary techniques for performing impedance matching are described. In an exemplary embodiment, the apparatus may include an amplifier (e. g. , a power amplifier) coupled to first and second matching circuits. The first matching circuit may include multiple stages coupled to a first node and may provide input impedance matching for the amplifier. The second matching circuit may include multiple stages coupled to a second node and may provide output impedance matching for the amplifier. At least one switch may be coupled between the first and second nodes and may bypass or select the amplifier. The first and second nodes may have a common impedance. The apparatus may further include a second amplifier coupled in parallel with the amplifier and further to the matching circuits. The second matching circuit may include a first input stage coupled to the amplifier, a second input stage coupled to the second amplifier, and a second stage coupled to the two input stages via switches.

US Patent:

20100291888, Nov 18, 2010

Filed:

Oct 7, 2009

Appl. No.:

12/575414

Inventors:

Aristotele Hadjichristos - Cary NC, US
Puay Hoe See - San Diego CA, US
Babak Nejati - San Diego CA, US
Guy Klemens - San Diego CA, US
Norman Frederick, JR. - Vista CA, US
Gurkanwal Singh Sahota - San Diego CA, US
Marco Cassia - San Diego CA, US
Nathan Pletcher - Encinitas CA, US
Yu Zhao - San Diego CA, US
Thomas Myers - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H04B 1/04

US Classification:

4551274

Abstract:

A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.

US Patent:

20100327976, Dec 30, 2010

Filed:

Feb 12, 2010

Appl. No.:

12/705493

Inventors:

Guy Klemens - San Diego CA, US
Thomas A. Myers - San Diego CA, US
Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US
Nathan M. Pletcher - Encinitas CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03F 3/16

US Classification:

330277

Abstract:

A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.

US Patent:

20110018632, Jan 27, 2011

Filed:

Nov 20, 2009

Appl. No.:

12/623248

Inventors:

Nathan Pletcher - San Diego CA, US
Aristotele Hadjichristos - San Diego CA, US
Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03F 1/56

US Classification:

330192

Abstract:

Exemplary embodiments are directed to a transmitter with a power amplifier and a switched output matching circuit implementing a plurality of output paths for a plurality of operating modes is described. The power amplifier receives an input RF signal and provides an amplified RF signal. An output matching network performs impedance transformation from low impedance at the power amplifier output to higher impedance at the matching network output. The plurality of output paths are coupled to the output matching network. Each output path provides a different target output impedance for the power amplifier and routes the amplified RF signal from the power amplifier to an antenna when that output path is selected. Each output path may include a matching network coupled in series with a switch. The matching network provides the target output impedance for the power amplifier when the output path is selected. The switch couples or decouples the output path to/from the power amplifier.

US Patent:

20110037519, Feb 17, 2011

Filed:

Feb 3, 2010

Appl. No.:

12/699659

Inventors:

Nathan M. Pletcher - San Diego CA, US
Yu Zhao - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03F 3/16

US Classification:

330277

Abstract:

Techniques for reducing distortion and improving linearity of amplifiers are described. In an exemplary design, an apparatus includes a driver amplifier, a variable matching circuit, and a power amplifier. The driver amplifier amplifies a first RF signal and provides a second RF signal. The variable matching circuit receives the second RF signal and provides a third RF signal. The power amplifier amplifies the third RF signal and provides a fourth RF signal. The variable matching circuit matches a fixed impedance at the output of the driver amplifier to a variable impedance at the input of the power amplifier in order to improve the linearity of the amplifiers. In an exemplary design, the power amplifier includes a first transistor (e.g., an NMOS transistor) of a first type, and the variable matching circuit includes a second transistor (e.g., a PMOS transistor) of a second type that is different from the first type.

US Patent:

20110043284, Feb 24, 2011

Filed:

Feb 24, 2010

Appl. No.:

12/711858

Inventors:

Yu Zhao - San Diego CA, US
Nathan M. Pletcher - Encinitas CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03F 3/16

US Classification:

330277

Abstract:

Techniques for improving linearity of amplifiers are described. In an exemplary design, an amplifier (e.g., a power amplifier) may include a plurality of transistors coupled in a stack and at least one diode. The plurality of transistors may receive and amplify an input signal and provide an output signal. The at least one diode may be operatively coupled to at least one transistor in the stack. Each diode may provide a variable bias voltage to an associated transistor in the stack. Each diode may have a lower voltage drop across the diode at high input power and may provide a higher bias voltage to the associated transistor at high input power. The at least one transistor may have higher gain at high input power due to the higher bias voltage from the at least one diode. The higher gain may improve the linearity of the amplifier.

US Patent:

20110316636, Dec 29, 2011

Filed:

Sep 6, 2011

Appl. No.:

13/226397

Inventors:

Yu Zhao - San Diego CA, US
Babak Nejati - San Diego CA, US
Nathan M. Pletcher - Encinitas CA, US
Aristotele Hadjichristos - , US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H03H 11/28
H03F 3/04

US Classification:

330310

Abstract:

A tunable inter-stage matching circuit that can improve performance is described. In an exemplary design, an apparatus comprises a driver amplifier and a power amplifier. The apparatus may further include an inter-stage matching circuit tunable in discrete steps for matching impedances between the driver amplifier and the power amplifier. The tunable inter-stage matching circuit may include a bank of capacitors, each capacitor of the bank coupled in series with a switch for coupling the capacitor to a ground voltage.