Zheng Z Xu

US Patent:

6368469, Apr 9, 2002

Filed:

May 6, 1997

Appl. No.:

08/851946

Inventors:

Jaim Nulman - Palo Alto CA
Sergio Edelstein - Los Gatos CA
Mani Subramani - San Jose CA
Zheng Xu - Foster City CA
Howard Grunes - Santa Cruz CA
Avi Tepman - Cupertino CA
John Forster - San Francisco CA
Praburam Gopalraja - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

20419212, 20429806, 20429808, 20429811

Abstract:

A sputtering coil for a plasma chamber in a semiconductor fabrication system is provided. The sputtering coil couples energy into a plasma and also provides a source of sputtering material to be sputtered onto a workpiece from the coil to supplement material being sputtered from a target onto the workpiece. Alternatively a plurality of coils may be provided, one primarily for coupling energy into the plasma and the other primarily for providing a supplemental source of sputtering material to be sputtered on the workpiece.

US Patent:

6372633, Apr 16, 2002

Filed:

Jul 8, 1998

Appl. No.:

09/111657

Inventors:

Dan Maydan - Los Altos Hills CA
Ashok K. Sinha - Palo Alto CA
Zheng Xu - Foster City CA
Liang-Yu Chen - Foster City CA
Roderick Craig Mosely - Pleasanton CA
Daniel Carl - Pleasanton CA
Diana Xiaobing Ma - Saratoga CA
Yan Ye - Campbell CA
Wen Chiang Tu - Sunnyvale CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438637, 257763

Abstract:

The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.

US Patent:

6387695, May 14, 2002

Filed:

Dec 22, 1998

Appl. No.:

09/218590

Inventors:

Robert K. Evans - Souderton PA
David B. Volkin - Doylestown PA
Mark W. Bruner - Norristown PA
Zheng Xu - Blue Bell PA

Assignee:

Merck Co., Inc. - Rahway NJ

International Classification:

C12N 1588

US Classification:

4353201, 435 691, 435325, 435455

Abstract:

The present invention relates to nucleic acid formulations of pharmaceutical products which comprise citrate and/or triethanolamine in concentrations which enhance stability of the nucleic acid. These formulations are suited for situations where prolonged storage occurs during the distribution and/or storage period prior to use.

US Patent:

6399479, Jun 4, 2002

Filed:

Aug 30, 1999

Appl. No.:

09/386077

Inventors:

Fusen Chen - Cupertino CA
Zheng Xu - Foster City CA
Peijun Ding - San Jose CA
Barry Chin - Saratoga CA
Ashok Sinha - Palo Alto CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 214763

US Classification:

438628, 438637, 438674

Abstract:

The invention provides a method for filling a structure on a substrate comprising: depositing a barrier layer on one or more surfaces of the structure, depositing a seed layer over the barrier layer, removing a portion of the seed layer, and electrochemically depositing a metal to fill the structure. Preferably, a portion or all of the seed layer formed on the sidewall portion of the structure is removed using a electrochemical de-plating process prior to the electroplating process.

US Patent:

6409890, Jun 25, 2002

Filed:

Jul 27, 1999

Appl. No.:

09/362917

Inventors:

Howard E. Grunes - Santa Cruz CA
Zheng Xu - Foster City CA
Praburam Gopalraja - Sunnyvale CA
John C. Forster - San Francisco CA
Ralf Hofmann - San Jose CA
Anantha Subramani - San Jose CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1435

US Classification:

20419212, 20429811, 20429812, 20429808, 20429826, 20429806, 20429819

Abstract:

Embodiments include devices and methods for sputtering material onto a workpiece in a chamber which includes a plasma generation area and a target. A coil is positioned to inductively couple energy into the plasma generation area to generate a plasma. A body is positioned between the workpiece and the target to prevent an amount of target material from being sputtered onto the workpiece. The body prevents an amount of target material from being sputtered onto the workpiece. The body may act as a dark space shield and inhibit plasma formation between the body and the target. The body may also act as a physical shield to block sputtered material from accumulating on the workpiece.

US Patent:

6413382, Jul 2, 2002

Filed:

Nov 3, 2000

Appl. No.:

09/705324

Inventors:

Wei Wang - Santa Clara CA
Praburam Gopalraja - Sunnyvale CA
Jianming Fu - San Jose CA
Zheng Xu - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1435

US Classification:

20419212, 20429808, 20429817, 2042982, 20429822

Abstract:

A magnetron sputter reactor having a target that is pulsed with a duty cycle of less than 10% and preferably less than 1% and further having a small magnetron of area less than 20% of the target area rotating about the target center, whereby a very high plasma density is produced during the pulse adjacent to the area of the magnetron. The power pulsing frequency needs to be desynchronized from the rotation frequency so that the magnetron does not overlie the same area of the magnetron during different pulses. Advantageously, the power pulses are delivered above a DC background level sufficient to continue to excite the plasma so that no ignition is required for each pulse.

US Patent:

6420127, Jul 16, 2002

Filed:

Oct 10, 1996

Appl. No.:

08/640877

Inventors:

Scott Hultgren - Ballwin MO
Meta Kuehn - Berkeley CA
Zheng Xu - Blue Bell PA
Derek Ogg - Uppsala, SE
Mark Harris - Uppsala, SE
Matti Lepisto - Lund, SE
Charles Hal Jones - Saint Louis MO
Jan Kihlberg - Dalby, SE

Assignee:

Washington University - St. Louis MO
Siga Pharmaceuticals, Inc. - Corvallis OR

International Classification:

G01N 33569

US Classification:

435 737, 4242411, 4242421, 4242571, 435849

Abstract:

Novel methods for the treatment and/or prophylaxis of diseases caused by tissue-adhering bacteria are disclosed. By interacting with periplasmic molecular chaperones it is achieved that the assembly of pili is prevented or inhibited and thereby the infectivity of the bacteria is diminished. Also disclosed are methods for screening for drugs as well as methods for the de novo design of such drugs, methods which rely on novel computer drug modelling methods involving an approximative calculation of binding free energy between macromolecules. Finally, novel pyranosides which are believed to be capable of interacting with periplasmic molecular chaperones are also disclosed.

US Patent:

6449525, Sep 10, 2002

Filed:

Apr 25, 2000

Appl. No.:

09/558457

Inventors:

Joanna Liu - Los Altos CA
Zheng Xu - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700121, 20419212

Abstract:

A multiple step process sputter deposits material of uniform thickness on stepped surfaces of an integrated circuit substrate such as the surfaces of a high aspect ratio via or a narrow trench. Material is first sputter deposited at the bottom of the opening at high pressure using a high power RF source connected to a coil in the deposition chamber to couple energy into the plasma. A high power RF bias is applied to the substrate, and a low power DC bias is applied to the sputtering target. The same parameters are repeated in a second step except that the high power RF bias on the substrate support is either reduced to a low power level or reduced to zero (by the end of the second step) to deposit on the lowest quarter of the sidewall of the opening. In a third step, no RF bias is applied to the pedestal remains and the pressure is reduced to a medium pressure state, resulting in a deposition on the second quarter of the sidewall of the opening. In a fourth step, the RF power coupled to the plasma is reduced to a low level, resulting in deposition on the third quarter of sidewall of the opening.